MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 986

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

NAND Boot Mode
12.12.1.9 Single Error Correct and Double Error Detect (SEC-DED)
For each 8-bit of data in the 512 byte FCB, 5-bit parity is used. Each byte of parity area
contains 5 parity bits (LSB) and 3 unused bits (MSB).
For each 8-bit of FCB data, parity is calculated and compared with the corresponding parity
bits read from the parity area of the FCB page to detect errors and correct any single error.
If there is more than one error, a flag is raised against the block.
To determine a good FCB, all three fingerprints must match and the ECC must not fail.
The data held in the FCB includes the following:
Additionally, the FCB is marked with three fingerprints in the sector.
12.12.1.10 Firmware Layout on the NAND
The boot image is typically located on the first good block after the FCB, DBBT blocks
and any additional blocks reserved for BCBs in case they go bad.
ROM shall support boot from only first NAND. In case of multi-NAND system, both
firmware copies should be located on first NAND, same as in the single-NAND system.
The DBBT will be located in its own search area and a copy of DBBT will be present at
each stride of the search area.
12.12.1.11 Recovery From a Failed Boot Firmware Image Read
The mechanism for recovering from a failed FCB read is covered in
(BCB). The SDK is warned about impending errors with the
NAND_SDK_BLOCK_REWRITE persistent bit and is notified of firmware boot errors
with the ROM_SECONDARY_BOOT persistent bit.
986
• NAND Timing parameters
• Geometry information (sectors per block, sectors per page, and so on)
• The page address of the discovered bad block table (DBBT)
• BCH ECC type
• A flag to boot the NAND patch image located at sector 2 of first block
• Starting page addresses of primary and secondary firmware
• Bad block marker bit offset in page data
Hamming
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Boot Control Blocks
Freescale Semiconductor, Inc.