MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1015

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.2.6.4.6 Buffer Size Field
The BUFFER_SIZE field (shown in the following table) indicates the size of the buffers
for memcopy, encryption, and hashing modes. For memcopy and hashing operations, the
value may be any number of bytes (byte granularity) and for encryption modes, the length
must be a multiple of the selected encryption algorithm's natural data size (16 bytes for
AES).
For blit operations, the buffer size field is split into two portions, a BLIT_WIDTH value,
which specifies the number of bytes in each line of the blit operation and a NUMBER_LINES
value, which specifies how many vertical rows of pixels are in the image buffer.
13.2.6.4.7 Payload Pointer
Some operations require additional control values that are stored in a Payload Buffer (shown
in the table below), which is pointed to by this field. After the DCP reads the control packet,
it examines the Control0 register and determines whether any payload information is required.
If so, the DCP loads the payload from the address specified in this field. (See
more details.)
The payload area is also written to by the DCP at the completion of a hash operation (when
the HASH_TERM) bit is set. Software must allocate the appropriate amount of storage (20
bytes for SHA-1 and 4 bytes for CRC32) in the payload or risk having the DCP write to an
unallocated address.
13.2.6.4.8 Status
After the DCP engine has completed processing a descriptor, it writes the packet status
(shown in the following table) back to the descriptor In the Status field. The packet status
is the value of the channel status register at the time the packet completed processing.
Freescale Semiconductor, Inc.
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NUMBER_LINES (blit mode)
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i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
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BUFFER_SIZE (in bytes, memcopy, encryption, hashing modes)
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Table 13-10. DCP Payload Buffer Pointer
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Table 13-9. DCP Buffer Size Field
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PAYLOAD_POINTER
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BLIT_WIDTH (in bytes, blit mode)
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Chapter 13 Data Co-Processor (DCP)
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Payload
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