MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1091

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 14 External Memory Interface (EMI)
14.6.1.1 Address Collision/Data Coherency Violation
The order in which read and write commands are processed in the memory controller is
critical for proper system behavior. While reads and writes to different addresses are
independent and may be re-ordered without affecting system performance, reads and writes
that access the same address are significantly related. If the port requests a read after a write
to the same address, then repositioning the read before the write would return the original
data, not the changed data. Similarly, if the read was requested ahead of the write but
accidentally positioned after the write, then the read would return the new data, not the
original data prior to being overwritten. These are significant data coherency mistakes.
To avoid address collisions, reads or writes that access the same chip select, bank and row
as a command already in the command queue will be inserted into the command queue after
the original command, even if the new command is of a higher priority.
This factor may be enabled/disabled through the addr_cmp_en parameter and should only
be disabled if the system can guarantee coherency of reads and writes.
14.6.1.2 Source ID Collision
Each port is assigned a specific source ID that is a combination of the port and thread ID
information, and identifies the source uniquely. This allows the memory controller to map
data from/to the correct source/destination.
Note that a source ID does contain port identification information, which means that the
rules for placement are dependent on the requesting port. There will not be source ID
collisions between ports.
In general, read commands from the same source ID will be placed in the command queue
in order. Therefore, a read command with the same source ID as a read command already
in the command queue will be processed after the original read command. All write
commands from a port, even with different source IDs, will be executed in order.
The behavior of commands of different types from the same source ID is dependent on the
user configuration. For this Memory Controller, the placement of new read/write commands
that collide in terms of source ID with existing entries in the command queue will only
depend on other commands of the same type, not on different types. This means that, if
there are no address conflicts, a read command could be executed ahead of a write command
with the same source ID, and likewise a write command could be executed ahead of a read
command with the same source ID.
This feature will always be enabled.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1091