MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1396
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
Programmable Registers
19.4.35 Debug Trap Range High Address for AHB Layer 0
The Debug Trap Range High Address Register defines the upper bound for an address range
that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs
within this range. This register applies only to AHB Layer 0.
This register sets the upper address that defines the debug trap function. When this function
is enabled, any active AHB cycle on Layer 0 which accesses this range will trigger an
interrupt to the ARM core.
EXAMPLE
Address:
Re-
19.4.36 Debug Trap Range Low Address for AHB Layer 3
The Debug Trap Range Low Address Register defines the lower bound for an address range
that can be enabled to trigger an interrupt to the ARM core when an AHB cycle occurs
within this range. This register applies only to AHB Layer 3.
This register sets the lower address that defines the debug trap function. When this function
is enabled, any active AHB cycle on Layer 3 which accesses this range will trigger an
interrupt to the ARM core.
EXAMPLE
1396
set
Bit
W
R
31
0
ADDR
Field
31 0
30
0
29
0
HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH
offset = 8001_C2D0h
(HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH)
(HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW)
28
0
HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH field descriptions
This field contains the 32-bit upper address for the debug trap range.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
ADDR
16
0
8001_C000h base + 2D0h
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0
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