MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1778

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
28.2.1 XTAL OSC Driving Mode
By default, every PWM channel outputs signals in XTAL OSC clock domain. It’s a 24 MHz
XTAL OSC.
By setting up two channels in lock step and by setting their low and high states to opposite
values, one can generate a differential signal pair that alternates between pulling to Vss and
floating to high-Z. By creating an appropriate offset in the settings of the two channels with
the same period and the same enables, one can generate differential drive pulses with digitally
guaranteed non-overlapping intervals suitable for controlling high-voltage switches.
In
is set for 1280 divided clocks for both channels. All active phases are set for 600 divided
clocks. There is a 40 divided clock guaranteed off-time between each active phase. Since
this is based on a crystal oscillator, it is a very stable non-overlapping period. The total
period is also a very stable crystal-oscillator-based time interval. In this example, the active
phases are pulled to Vss (ground), while the inactive phases are allowed to float to a high-Z
state.
1778
Figure
HW_PWM_ACTIVE0_ACTIVE = 0
HW_PWM_ACTIVE0_INACTIVE = 600
HW_PWM_PERIOD0_ACTIVE_STATE = 10
HW_PWM0BR_INACTIVE_STATE = 00
HW_PWM_PERIOD0_PERIOD = 1280
PWM0 Output
PWM1 Output
ACTIVE_FF1
ACTIVE_FF0
28-3, a differential pair is established using Channel 0 and Channel 1. The period
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 28-3. PWM Differential Output Pair Example
600
640
40
guaranteed
digitally
680
600
hi-Z
40
HW_PWM_PERIOD1= 1280
HW_PWM_ACTIVE1 = 640
HW_PWM_INACTIVE1 = 1240
HW_PWM_ACTIVE1_STATE = 10
HW_PWM_INACTIVE1_STATE = 00
Freescale Semiconductor, Inc.
Vss