MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2247

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 37 High-Speed ADC (HSADC)
37.3.7 Interrupt Sources
There are two ways for ARM CPU to talk with the high-speed ADC block. One is by polling
the interrupt bit in HSADC Control Register 1. The other is by interrupt. The ARM can
choose one of these two modes by configure register. The user can enable the interrupt so
that when one sequence is done, the interrupt is asserted. and when the asynchronous FIFO
overflow occurs, the FIFO_OVERFLOW interrupt is asserted. Normally, the FIFO overflow
will seldom occur because the APBH-DMA is working on 200 MHz clock frequency and
the maximum sampling rate is 2 Msps for 12-bit sample data which means that the maximum
data rate is 1 MHz word. So, the bandwidth of DMA should be enough to avoid the FIFO
overflow. When overflow occurs, the FIFO will discard 16 words of sample data and then
continues working. There is TIMEOUT interrupt which will be asserted when the block is
pending. When the ARM CPU enters into interrupt mode, it should first clear the interrupt
by setting INTERRUPT_CLR bit. Then, check the HSADC Control Register 1 for the
interrupt status. Then, set INTERRUPT_STATUS_CLR bit to clear the interrupt status bits.
37.3.8 Working Modes
There are two working modes for HSADC. When the value set to HSADC Sequence Number
Register is 1, the HSADC is working in single mode; When the value set to HSADC
Sequence Number Register is not 1, the HSADC is working in loop mode.
37.3.8.1 Single Mode
For single mode, the HSADC just captures one sequence of sample data. The number of
sample data need to be captured can be controlled by configuring the HSADC Sequence
Samples Number Register. Note that when set the value of HSADC Sequence Samples
Number Register as 0, it means endless capturing of samples till the disassertion of
HSADC_RUN bit in HSADC Control Register 0.
37.3.8.2 Loop Mode
For loop mode, the HSADC will capture more than one sequence of sample data. The
number of samples for each sequence can be configured just the same as single mode. When
one sequence is finished, the HSADC will automatically enter the state to wait for the next
trigger pulse to start the next sequence of sampling. The number of sequences can be
configured in HSADC Sequence Number Register. Please note that when set the value of
HSADC Sequence Number Register as 0, it means endless capture of sequences till the
disassertion of HSADC_RUN bit in HSADC Control Register 0.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
2247