MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1734

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
27.2.2.1 Simple Device Transactions
The simplest transfer of interest on an I
to a slave, for example, writing a single byte to an FM tuner. In this transaction, a start
condition is transmitted, followed by the device address byte, followed by a single byte of
write data. This sequence always ends with a stop condition.
Table 27-3
single byte write operation, ST is a start condition, and SP is a stop condition. The data
transfer occurs between these two bus events. It starts with a slave address plus write byte
(SAD+W) addressing the targeted slave. A slave-generated acknowledge bit (SAK) tells
the master that a slave has recognized the address and will accept the transfer. The master
sends the data byte (DATA), and the slave acknowledges it with an SAK.
1734
ST
DATA
SAD
SUB
Table 27-2. I
SAK
BIT
SR
ST
defines the symbols used in describing I
SCLoe
SDAin
SCLin
Table 27-3. I
Slave
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 27-3. I
2
C Transfer When the Interface is Transmitting as a Master
Start Condition
Repeated Start Condition
Slave Address
Slave Acknowledge
Sub-Address, e.g., for EEPROMs
Data
Description
T
Bit 2
DHD
Low clk
SAD+W
2
C Slave and Master Mode Address Definitions
Bit 1
High clk
2
C Data and Clock Timing Generation
Master
2
C bus is writing a single data byte from a master
T
DSU
SAK
Grab
Read
Data
Bit 0
2
C transactions. For example, in the
Change
Write
Data
DATA
SAK
Hold Clock
Freescale Semiconductor, Inc.
SAK
SP