MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1666

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
26.4.6 ENET MAC MII Management Frame Register
MDIO Management Register
Performing a write to the MMFR register triggers a management frame transaction to the
PHY device unless the MSCR is programmed to 0. If the MSCR register is written to a
non-zero value in the case of writing to MMFR when MSCR equals 0, an MII frame is
generated with the data previously written to the MMFR. This allows MMFR and MSCR
to be programmed in either order if MSCR is currently zero. If the MMFR register is written
while frame generation is in progress, the frame contents are altered. Software must use the
EIR(MII) interrupt indication to avoid writing to the MMFR register while frame generation
is in progress.
1666
MAGIC_ENA
ETHER_EN
ENA_1588
RESET
SLEEP
Field
4
3
2
1
0
(HW_ENET_MAC_MMFR)
IEEE1588 Enable. Should be set to '1' to enable the Frame Time Stamping functions. Also drives the DMA
control bit ena_1588.
Put controller in Sleep Mode. When asserted (Set to 1) the controller is configured in sleep mode. When set
to 0 (Reset value) the controller is in normal operating mode.
Enable Magic Packet Detection. When set to 1, the controller detects Magic Packets and will assert the EIR
(WAKEUP) bit when a frame is detected.
When set to 0 (Reset value) the Magic Detection logic is disabled.
Note: MAGIC_ENA is relevant only if the SLEEP bit is 1. If set to 1, changing the SLEEP bit will enable or
disable both sleep mode and magic packet detection.
When this bit is set, MAC is enabled, and reception and transmission are possible. When this bit is cleared,
reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted
frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When
ETHER_EN is cleared, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer
descriptor and FIFO pointers. Hardware alters the ETHER_EN bit under the following conditions:
RESET is set by software, in which case ETHER_EN is cleared
An error condition causes the EBERR bit to set, in which case ETHER_EN is cleared
The behavior of ENET-MAC when set this bit is depend on Switch mode.
If disable switch, assert this bit will reset MAC and UDMA. If enable switch, assert this bit will only reset
MAC. UDMA will be reset by software reset of switch.
HW_ENET_MAC_ECR field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.