MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1563

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

For the regular mailbox MBs, an MB is said to be free to receive a new frame if the following
conditions are satisfied:
If the first MB with a matching ID is not free to receive the new frame, then the matching
algorithm keeps looking for another free MB until it finds one. If it can not find one that is
free, then it will overwrite the last matching MB (unless it is locked) and set the Code field
to OVERRUN (see
new message remains in the SMB, waiting for the MB to be unlocked (see
Lock
Suppose, for example, the FIFO is disabled and there are two MBs with the same ID, and
FlexCAN starts receiving messages with that ID. Let us say that these MBs are the second
and the fifth in the array. When the first message arrives, the matching algorithm will find
the first match in MB number 2. The code of this MB is EMPTY, so the message is stored
there. When the second message arrives, the matching algorithm will find MB number 2
again, but it is not free to receive, so it will keep looking and find MB number 5 and store
the message there. If yet another message with the same ID arrives, the matching algorithm
finds out that there are no matching MBs that are free to receive, so it decides to overwrite
the last matched MB, which is number 5. In doing so, it sets the Code field of the MB to
indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a
reception queue (in addition to the full featured FIFO) to allow more time for the ARM to
service the MBs. By programming more than one MB with the same ID, received messages
will be queued into the MBs. The ARM can examine the Time Stamp field of the MBs to
determine the order in which the messages are arrived.
The matching algorithm described above can be changed to be the same one used in previous
versions of the FlexCAN module. When the BCC bit in MCR is negated, the matching
algorithm stops at the first MB with a matching ID that it founds, whether this MB is free
or not. As a result, the message queueing feature does not work if the BCC bit is negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports
individual masking per MB. During the matching algorithm, if a mask bit is asserted, then
the corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit
is "don't care". The Individual Mask Registers are implemented in RAM, so they are not
initialized out of reset. Also, they can only be programmed if the BCC bit is asserted and
while the module is in Freeze Mode.
Freescale Semiconductor, Inc.
• The MB is not locked (see
• The Code field is either EMPTY or it is FULL or OVERRUN but the ARM has already
serviced the MB (read the C/S word and then unlocked the MB)
Mechanism).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 25-2
and
Message Buffer Lock
Table
25-3). If the last matching MB is locked, then the
Mechanism)
Chapter 25 Controller Area Network (FlexCAN)
Message Buffer
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