MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1605

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.2.2.31.23.3
See
26.2.2.31.23.4
application software to indicate that the frame stored in the system memory contains an
error. This bit is valid regardless of if the L-bit is set and must be the same for all EBD for
a given frame. The uDMA does not update this value.
26.2.2.31.23.5
uDMA is to generate a dma_int_txb / dma_int_txf interrupt in relation to this frame / buffer
descriptor. This bit is valid regardless of if the L-bit is set and must be the same for all EBD
for a given frame. The uDMA does not update this value.
26.2.2.31.23.6
Timestamp. This bit is written by the user. This indicates that the uDMA is to generate a
timestamp frame. This bit is valid regardless of if the L-bit is set and must be the same for
all EBD for the given frame. The uDMA does not update this value.
26.2.2.31.23.7
Insert protocol specifc checksum. This bit is written by the user. If '1' the MAC's IP
accelerator calculates the protocol checksum and overwrites the corresponding checksum
feld with the calculated value. The checksum feld must be set to 0 by the application
generating the frame. The uDMA does not update this value. This bit is valid regardless of
if the L-bit is set and must be the same for all EBD for a given frame.
26.2.2.31.23.8
Insert IP header checksum. This bit is written by the user. If '1' the MAC's IP accelerator
calculates the IP header checksum and overwrites the corresponding header feld with the
calculated value. The checksum feld must be set to 0 by the application generating the
frame. The uDMA does not update this value. This bit is valid regardless of if the L-bit is
set and must be the same for all EBD for a given frame.
26.2.2.31.23.9
that there was a transmit error reported with the frame. Effectively this bit is the "or" of all
other error bits including UE, EE, FE, LCE, OE, and TSE. This bit is only valid when the
L-bit is set.
Freescale Semiconductor, Inc.
Legacy FEC Transmit Buffer
Offset + 4 and Offset + 6 - TX Data Buffer Pointer
This functionality does not change from the legacy programming model.
Offset + 8 Bit 15 "-"
Error Indication. This bit is written by the user. This bit is used by the
Offset + 8 Bit 14 "INT"
Generate interrupt. This bit is written by the user. This indicates that the
Offset + 8 Bit 13 "TS"
Offset + 8 Bit 12 "PINS"
Offset + 8 Bit 11 "IINS"
Offset + A Bit 15 "TXE"
Transmit error occurred. This bit is written by the uDMA. This bit indicates
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Descriptor.
Chapter 26 Ethernet Controller (ENET)
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