MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 882

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
10.8.21 ENET Clock Control Register (HW_CLKCTRL_ENET)
This register provides control for ETHERNET clock generation
EXAMPLE
HW_CLKCTRL_ENET_WR(BF_CLKCTRL_ENET_SLEEP(1));
Address:
882
Reset
Reset
DIV_FRAC_EN
Bit
Bit
W
W
RSRVD1
R
R
BUSY
Field
28 8
6 0
DIV
29
7
31
15
1
0
HW_CLKCTRL_ENET
30
14
1
0
This read-only bit field returns a one when the clock divider is busy transfering a new divider value across
clock domains.
Always set to zero (0).
1 = Enable fractional divide. 0 = Enable integer divide.
The ETM clock frequency is determined by dividing the selected reference clock (ref_xtal or ref_cpu) by the
value in this bit field. This field can be programmed with a new value only when CLKGATE = 0.
NOTE: The divider is set to divide by 1 at power-on reset. Do NOT divide by 0.
29
13
1
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CLKCTRL_ETM field descriptions (continued)
28
12
0
0
8004_0000h base + 140h offset = 8004_0140h
27
11
0
0
26
10
0
0
25
0
0
9
DIV_TIME
24
0
RSRVD0
0
8
Description
23
0
0
7
22
0
0
6
21
0
5
0
TIME_SEL
20
1
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0