MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2322

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Examples
39.5.1 Setting 1-Bit Wide Field
// Preferred (one atomic write to SET register)
HW_GPMI_CTRL0_SET(BM_GPMI_CTRL0_UDMA);
// Alternate (same as above, just different syntax)
BF_SET(GPMI_CTRL0, UDMA);
// Avoid
BW_GPMI_CTRL0_UDMA(1);
BF_WR(GPMI_CTRL0, UDMA, 1);
HW_GPMI_CTRL0.B.UDMA = 1;
39.5.2 Clearing 1-Bit Wide Field
// Preferred (one atomic write to _CLR register)
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_DEV_IRQ_EN);
// Alternate (same as above, just different syntax)
BF_CLR(GPMI_CTRL0, DEV_IRQ_EN);
// Avoid
BW_GPMI_CTRL0_DEV_IRQ_EN(0);
BF_WR(GPMI_CTRL0, DEV_IRQ_EN, 0);
HW_GPMI_CTRL0.B.DEV_IRQ_EN = 0;
39.5.3 Toggling 1-Bit Wide Field
// Preferred (one atomic write to _TOG register)
HW_GPMI_CTRL0_TOG(BM_GPMI_CTRL0_RUN);
// Alternate (same as above, just different syntax)
BF_TOG(GPMI_CTRL0, RUN);
// Avoid
HW_GPMI_CTRL0.B.RUN ^= 1;
39.5.4 Modifying n-Bit Wide Field
// Preferred (does CS operation or byte/halfword write if the field is
//
BW_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE);
BW_GPMI_CTRL0_COMMAND_MODE(iMode);
BW_GPMI_CTRL0_XFER_COUNT(2);
// Alternate (same as above, just different syntax)
BF_WR(GPMI_CTRL0, COMMAND_MODE, BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE);
BF_WR(GPMI_CTRL0, COMMAND_MODE, iMode);
BF_WR(GPMI_CTRL0, XFER_COUNT, 2);
// Avoid (RMW)
HW_GPMI_CTRL0.B.COMMAND_MODE = BV_GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE;
HW_GPMI_CTRL0.B.COMMAND_MODE = iMode;
39.5.5 Modifying Multiple Fields
// Preferred (explicit CS operation)
HW_GPMI_CTRL0_CLR( OR3(BM_GPMI_CTRL0, RUN, DEV_IRQ_EN, COMMAND_MODE) );
2322
8 or 16 bits wide and properly aligned)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
// writes 1 to _CLR then 1 to _SET register
// same as above, just different syntax
// RMW
// writes 1 to _CLR then 0 to _SET register
// this does a halfword write
// this does a halfword write
// same as above, just different syntax
// RMW
// RMW
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