MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 823

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

9.4.69 PINCTRL Bank 1 Interrupt Level/Edge Register
The PINCTRL Bank 1 Interrupt Level/Edge Register selects level or edge sensitivity for
interrupt requests for the pins in bank 1.
HW_PINCTRL_IRQLEVEL1: 0x1210
HW_PINCTRL_IRQLEVEL1_SET: 0x1214
HW_PINCTRL_IRQLEVEL1_CLR: 0x1218
HW_PINCTRL_IRQLEVEL1_TOG: 0x121C
This register selects level or edge detection for interrupt generation. Each pin in bank 1 that
is configured for interrupt generation can be independently set to interrupt on low level,
high level, rising edge, or falling edge by setting bits in this register and
HW_PINCTRL_IRQPOL1 (see below) appropriately.
Address:
Re-
9.4.70 PINCTRL Bank 2 Interrupt Level/Edge Register
The PINCTRL Bank 2 Interrupt Level/Edge Register selects level or edge sensitivity for
interrupt requests for the pins in bank 2.
HW_PINCTRL_IRQLEVEL2: 0x1220
HW_PINCTRL_IRQLEVEL2_SET: 0x1224
HW_PINCTRL_IRQLEVEL2_CLR: 0x1228
Freescale Semiconductor, Inc.
set
Bit
W
R
IRQLEVEL
31
0
Field
31 0
30
0
29
0
(HW_PINCTRL_IRQLEVEL1)
(HW_PINCTRL_IRQLEVEL2)
HW_PINCTRL_IRQLEVEL1
28
0
Each bit in this register corresponds to one of the 32 pins in bank 1:
1= Level detection;
0= Edge detection.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_PINCTRL_IRQLEVEL1 field descriptions
24
0
23
0
22
0
21
0
8001_8000h base + 1210h offset = 8001_9210h
20
0
19
0
18
0
17
0
IRQLEVEL
16
0
15
0
Description
14
0
13
0
12
0
11
0
Chapter 9 Pin Control and GPIO (PinCtrl)
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
823
0
0