MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2218

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
35.3.3 SAIF Data Register (HW_SAIF_DATA)
The SAIF Data Register is used to either write PCM data samples to the top of the SAIF
FIFOs for transmit, or read PCM samples from the bottom of the FIFOs during receive.
32-bit values written/read to/from this register contain either one 17-bit to 24-bit sample or
two 16-bit samples.
HW_SAIF_DATA: 0x020
HW_SAIF_DATA_SET: 0x024
HW_SAIF_DATA_CLR: 0x028
HW_SAIF_DATA_TOG: 0x02C
In transmit mode, writing a value to this register causes it to push the value to the top of the
FIFO. In receive mode, reads cause values to be popped from the bottom of the FIFO.
Writing to a full FIFO does not change the contents of the FIFO's top entry, and reading
from an empty FIFO returns all zeros. For 16-bit operation, the left sample should be written
to the register's lower half word, and the right to the upper half word. For all other data
sizes, PCM audio values should be right-justified within the 32-bit word. Three FIFOs exist,
one for each channel pair. If two-channel operation is enabled, only the stereo or front FIFO
is accessed. Four-channel opearation causes both the front and surround FIFOs to be accessed.
Six-channel operation uses all three FIFOs: front, surround, and center/LFE FIFOs. For
both transmit and receive FIFO accesses, left and right samples should be interleaved,
starting with all left samples for a given sample time, followed by all right samples (e.g.,
left front, left surround, center, right front, right surround, LFE (subwoofer), and so on).
Operation should always start with the left samples. All left or all right channels for a given
sample collection in time are received/transmitted simultaneously (e.g., for 6-channel mode,
three PCM audio samples are popped from the FIFO prior to serialization and transmission).
For mono operation, use the left channel to transmit/receive PCM audio, while the right
channel should be zero-filled (TX) or discarded (RX). For transmit, if the FIFO is empty
when operation begins, null (zero) data is output until the FIFO contains valid PCM data.
2218
RSRVD0
BUSY
Field
3 1
0
Reserved.
This bit indicates when the SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s).
For transmit, it is automatically set when the first sample from the FIFO begins to be output by the serial
shifter. For receive, it is set coincident with the RUN bit beging set as serial receive begins immediately.
After the RUN bit is cleared and the serial shifter becomes inactive (end of the current sample set), this bit
is automatically cleared.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SAIF_STAT field descriptions (continued)
Description
Freescale Semiconductor, Inc.