MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1244

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

GPMI NAND Mode
For example, a NAND with tREAmax=20 ns, tRPmin=12 ns, and tRCmin=25 ns (read
cycle time) may be programmed as follows:
15.2.5 NAND Command and Address Timing Example
The following figure illustrates a command and address being sent to a NAND Flash.
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• GPMICLK clock frequency: Consider 480/6=80 MHz which is 12.5 ns clock period.
• Since (tREA +4 ns) is greater than tRP, required DELAY = tREA+4 ns - tRP = 20 + 4
• HALF_PERIOD =0, since GPMICLK period is less than 16 ns. So RP=GPMICLK
• DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x RP.9.42 ns =
This is too close to the minimum NAND spec if we program the data setup and hold
to 1 GPMICLK cycle. Consider 480/7=68.57 MHz which is 14.58 ns clock period.
With data setup and hold set to 1, we have a tRP of 14.58 ns and a tRC of 29.16 ns
(good margins).
- 14.58 ns = 9.42 ns.
period = 14.58 ns.
HW_GPMI_CTRL1_RDN_DELAY x 0.125 x 14.58
ns.HW_GPMI_CTRL1_RDN_DELAY = 5 (round off 5.169)
It is recommended that the drive strength of GPMI_RDn and
GPMI_WRn output pins be set to 8 mA. This will reduce the
transition time under heavy loads. Low transition times will be
important when NAND interface read and write cycle times are
below 30 ns. The other GPMI pins may remain at 4 mA, since
their frequency is only up to half that of GPMI_RDn and
GPMI_WRn.
Figure 15-4. NAND Command and Address Timing Example
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
GPMI_DATA
GPMI_CEn
GPMI_CLE
GPMI_ALE
GPMI_WEn
Run=1
TAS
read cmd
TDS
$00
TDH
Run=0
Note
Run=1
TAS
TDS
AL[7:0]
TDH
AL[15:8]
TDH
Run=0
Freescale Semiconductor, Inc.