MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1564

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Functional Description
FlexCAN also supports an alternate masking scheme with only three mask registers
(RGXMASK, RX14MASK and RX15MASK) for backwards compatibility. This alternate
masking scheme is enabled when the BCC bit in the MCR Register is negated.
25.4.6 Data Coherence
In order to maintain data coherency and FlexCAN proper operation, the ARM must obey
the rules described in
a MB structure within FlexCAN other than those specified may cause FlexCAN to behave
in an unpredictable way.
25.4.6.1 Transmission Abort Mechanism
The abort mechanism provides a safe way to request the abortion of a pending transmission.
A feedback mechanism is provided to inform the ARM if the transmission was aborted or
if the frame could not be aborted and was transmitted instead. In order to maintain backwards
compatibility, the abort mechanism must be explicitly enabled by asserting the AEN bit in
the MCR.
In order to abort a transmission, the ARM must write a specific abort code (1001) to the
Code field of the Control and Status word. When the abort mechanism is enabled, the active
MBs configured as transmission must be aborted first and then they may be updated. If the
abort code is written to a MB that is currently being transmitted, or to an MB that was
already loaded into the SMB for transmission, the write operation is blocked and the MB
is not deactivated, but the abort request is captured and kept pending until one of the
following conditions is satisfied:
If none of conditions above are reached, the MB is transmitted correctly, the interrupt flag
is set in the IFLAG register and an interrupt to the ARM is generated (if enabled). The abort
request is automatically cleared when the interrupt flag is set. In the other hand, if one of
the above conditions is reached, the frame is not transmitted, therefore the abort code is
written into the Code field, the interrupt flag is set in the IFLAG and an interrupt is
(optionally) generated to the ARM.
1564
• The module loses the bus arbitration
• There is an error during the transmission
• The module is put into Freeze Mode
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Transmit Process
and
Receive
Process. Any form of ARM accessing
Freescale Semiconductor, Inc.