MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1597

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.2.2.1 Legacy Buffer Descriptor Models
Table 26-1
26.2.2.1.1 Legacy FEC Receive Buffer Descriptor
This section discusses the legacy FEC receive buffer descriptors.
The following sections reference
26.2.2.1.1.1
operation of this bit does not change from the FEC. The uDMA clears this bit to indicate
that the buffer descriptor is complete and ready for the driver to process.
26.2.2.1.1.2
read/write bit will not be modified by hardware, nor will its value affect hardware.
26.2.2.1.1.3
change from the FEC. It indicates the next buffer descriptor the uDMA is supposed to use.
If 0 the next buffer descriptor is found in the consecutive location, and if 1 the next buffer
descriptor is found at the location defined in ERDSR.
26.2.2.1.1.4
read/write bit will not be modified by hardware, nor will its value affect hardware.
26.2.2.1.1.5
buffer descriptor is the last buffer descriptor in the frame.
26.2.2.1.1.6
Freescale Semiconductor, Inc.
Offset + 0
Offset + 2
Offset + 4
Offset + 6
and
Bit-15 E
Empty. Written by the uDMA (=0) and user (=1). The functionality and
Bit-14 RO1
Receive software ownership. This field is reserved for use by software. This
Bit-13 W
Wrap. Written by user. The functionality and operation of this bit does not
Bit-12 RO2
Receive software ownership.This field is reserved for use by software. This
Bit-11 L
Last in frame. Written by the uDMA. Setting this bit to '1' indicates that the
Bit-10 and Bit 9
These bits are reserved and must not be modified.
Table 26-2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
15
Table 26-1. Legacy FEC Receive Buffer Descriptor
E
RO1
14
show the legacy buffer descriptor (LBD) models.
13
W
RO2
12
Table
11
L
26-1.
10
—
RX Data Buffer Pointer - A[31:16]
RX Data buffer Pointer - A[15:0]
—
9
Data length
M
8
BC
7
MC
6
Chapter 26 Ethernet Controller (ENET)
LG
5
NO
4
—
3
CR
2
OV
1
1597
TR
0