MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1630

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

MAC Transmit
• FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X
4 +X 2 +X 1 +1
The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the
right-most bit of the first octet. The CRC bits are thus transmitted in the following order:
X31, X30,..., X1, X0.
26.3.8.5 Inter Packet Gap
In full duplex mode, after frame transmission and before transmission of a new frame, an
Inter Packet Gap (IPG), programmed with register TX_IPG_LENGTH, is maintained. The
minimum IPG can be programmed to any value between 8 and 27 byte-times (64 and 216
bit-times).
In half duplex mode, the core constantly monitors the line. Actual transmission of the data
onto the network occurs only if it has been idle for a 96-bit time period and any backoff
time requirements have been satisfied. In accordance with the standard, the Core begins to
measure the IPG from mii_crs / gmii_crs de-assertion.
26.3.8.6 Collision Detection and Handling - Half Duplex Operation Only
A collision occurs on a half-duplex network when concurrent transmissions from two or
more nodes take place. During transmission, the Core monitors the line condition and detects
a collision when the PHY device asserts the MII mii_col signal.
When the Core detects a collision while transmitting, it stops the transmission of data and
transmits a 32-bit jam pattern. If the collision is detected during the preamble or the SFD
transmission, the jam pattern is transmitted after completing the SFD, which results in a
minimum 96-bit fragment. The jam pattern is a fixed pattern that is not compared to the
actual frame CRC and has a very low probability (0.532) of having a jam pattern identical
to the CRC.
If a collision occurs before the transmission of 64 bytes (Including preamble and SFD), the
MAC Core waits for the backoff period and retransmits the packet data (Stored in a 64-Bytes
re-transmit buffer) already sent on the line. The backoff period is generated from a pseudo
random process (Truncated binary exponential backoff).
If a collision occurs after the transmission of 64 bytes (Including preamble and SFD), the
MAC discards the remaining of the Frame, optionally sets the interrupt bit LC and sets the
transmit status bit tx_ts_stat(1).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
1630
Freescale Semiconductor, Inc.