MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 40

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Section Number
40
15.3
15.4
16.1
16.2
Behavior During Reset................................................................................................................................................1245
Programmable Registers.............................................................................................................................................1245
BCH Overview............................................................................................................................................................1259
Operation....................................................................................................................................................................1261
15.2.3
15.2.4
15.2.5
15.2.6
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.4.9
15.4.10
15.4.11
15.4.12
15.4.13
16.2.1
16.2.2
16.2.3
16.2.4
Basic NAND Timing...............................................................................................................................1242
High-Speed NAND Timing.....................................................................................................................1242
NAND Command and Address Timing Example....................................................................................1244
Hardware BCH Interface.........................................................................................................................1245
GPMI Control Register 0 (HW_GPMICTRL0)......................................................................................1246
GPMI Compare Register (HW_GPMICOMPARE)................................................................................1248
GPMI Integrated ECC Control Register (HW_GPMIECCCTRL).........................................................1248
GPMI Integrated ECC Transfer Count Register (HW_GPMIECCCOUNT)..........................................1250
GPMI Payload Address Register (HW_GPMIPAYLOAD).....................................................................1250
GPMI Auxiliary Address Register (HW_GPMIAUXILIARY)...............................................................1251
GPMI Control Register 1 (HW_GPMICTRL1)......................................................................................1251
GPMI Timing Register 0 (HW_GPMITIMING0)...................................................................................1253
GPMI Timing Register 1 (HW_GPMITIMING1)...................................................................................1254
GPMI DMA Data Transfer Register (HW_GPMIDATA).......................................................................1254
GPMI Status Register (HW_GPMISTAT)...............................................................................................1255
GPMI Debug Information Register (HW_GPMIDEBUG).....................................................................1257
GPMI Version Register (HW_GPMIVERSION)....................................................................................1258
BCH Limitations and Assumptions.........................................................................................................1262
Flash Page Layout...................................................................................................................................1263
Determining the ECC layout for a device...............................................................................................1264
Data Buffers in System Memory.............................................................................................................1266
16.2.3.1
16.2.3.2
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
4K+218 flash, 10 bytes metadata, 512 byte data blocks, separate metadata........................1264
4K+128 flash, 10 bytes metadata, 512 byte data blocks, separate metadata........................1265
20-BIT Correcting ECC Accelerator (BCH)
Chapter 16
Title
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