MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2213

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

HW_SAIF_CTRL_SET: 0x004
HW_SAIF_CTRL_CLR: 0x008
HW_SAIF_CTRL_TOG: 0x00C
The SAIF Control Register is used to configure the SAIF's input/output frame format,
MCLK, BITCLK and LRCLK, and interrupt enables.
EXAMPLE
HW_SAIF_CTRL.RUN = 1; // start SAIF operation
Address:
Freescale Semiconductor, Inc.
Reset
Reset
BITCLK_MULT_
CLKGATE
Bit
Bit
W
W
SFTRST
R
R
29 27
RATE
Field
31
30
CHANNEL_
31
15
1
SELECT
0
NUM_
HW_SAIF_CTRL
30
14
1
0
Setting this bit to 1 forces a reset to the entire block. SFTRST has no effect on CLKGATE. Also, the SFTRST
bit may be written when CLKGATE=1. This bit must be cleared to 0 for normal operation.
This bit gates the clocks to the SAIF to save power when the clocks are not in use. When set to 1, this bit
gates off the clocks to the block. When this bit is cleared to 0, the block receives its clocks for normal
operation.
BITCLK Mutiplier Rate. This bit field selects the multiple of the base frequency rate of BITCLK for transmit
mode and receive master clock mode (READ_MODE=1, SLAVE_MODE=0), or if the alternate BITCLK pin
is used, it selects the multiple of the base frequency rate of MCLK (any mode).
When BITCLK_BASE_RATE = 0 (32x base rate): 000=512 x Fs, 001=256 x Fs, 010=128 x Fs, 011=64 x
Fs, 100=32 x Fs, 101-111=reserved.
When BITCLK_BASE_RATE = 1 (48x base rate): 000=384 x Fs, 001=192 x Fs, 010=96 x Fs, 011=48 x Fs,
100-111=reserved.
When the SAIF_BITCLK_MCLK pin is used as BITCLK, this field should be programmed to 32x for 16-bit
data, 48x for 16-bit to 24-bit data (BITCLK_48XFS_ENABLE=1), and 64x for 17-bit to 24-bit data, depending
on the modes supported by the off-chip codec.
29
13
BITCLK_MULT_
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RATE
28
12
0
0
8004_2000h base + 0h offset = 8004_2000h
HW_SAIF_CTRL field descriptions
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
Description
23
0
0
7
WORD_LENGTH
RSRVD2
22
0
0
6
Chapter 35 Serial Audio Interface (SAIF)
21
0
5
0
20
0
4
0
DMAWAIT_COUNT
19
0
0
3
18
0
0
2
17
0
0
1
RUN
2213
16
0
0
0