MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1167

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.66 DRAM Control Register 71 (HW_DRAM_CTL71)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
PHY_CTRL_
TDFI_PHY_
REG_0_0
31
0
RSVD1
RDLAT
Field
Field
31 0
7 4
3 0
30
0
29
0
HW_DRAM_CTL71
28
0
If phy_ctrl_reg_2 [25] = 1:
If (tdfi_rddata_en_base + rdlat_adj) < 4:
tdfi_rddata_en = reg_dimm_enable
If (tdfi_rddata_en_base + rdlat_adj) >= 4:
tdfi_rddata_en = tdfi_rddata_en_base + rdlat_adj + reg_dimm_enable - RDLAT_WIDTH'h4
This parameter is read-only.
Always write zeroes to this field.
Holds the tPHY_RDLAT timing parameter.
Holds the tphy_rdlat timing parameter.
Controls pad output enable times and other PHY parameters for data slice 0.
There is a separate phy_ctrl_reg_0_X parameter for each of the slices of data sent on the DFI data bus.
Bit [31] = Enables dynamic termination select in the PHY for the DM pads.
'b0 = Disabled
'b1 = Enabled
Bit [29] = Controls termination enable for the DM pads. Set to 'b1 to disable termination.
'b0 = Enabled
'b1 = Disabled
Bits [28] = Echo gate control for data slice X. Default 0x0.
'b0 = Uses the dfi_rddata_en signal to create a gate.
'b1 = Creates an echo_gate signal.
Bit [27] = Gather FIFO Enable
'b0 = Disabled
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL70 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL71 field descriptions
800E_0000h base + 11Ch offset = 800E_011Ch
22
0
21
0
20
0
19
0
PHY_CTRL_REG_0_0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1167
0
0