MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1640

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Resets and Stop Controls
26.3.12.4 Graceful Transmit Stop (GTS)
When gracefully stopped, the MAC is no longer reading frame data from the transmit FIFO
and has completed any ongoing transmission. In any of the following conditions, the transmit
datapath will stop after an ongoing frame transmission has been completed normally.
When the transmitter has reached its stopped state, the following events occur:
26.3.12.5 Graceful Receive Stop (GRS)
When gracefully stopped, the MAC is no longer writing frames into the receive FIFO. If
any of the following conditions occur, the receive datapath will stop after any ongoing frame
reception has been completed normally.
When the receive datapath is stopped, the following events will occur:
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• Register bit TCR(GTS) is set by software.
• Register bit TCR(TFC_PAUSE) is set by software requesting a pause frame transmission.
• A pause frame was received stopping the transmitter. The stopped situation is terminated
• MAC is placed in Sleep mode by set
• The GRA interrupt is asserted (once, when transitioned into stopped).
• MAC is placed in sleep mode (by set
• The RCR(GRS) bit is set as long as the RX is in the stopped state.
• The GRA interrupt is asserted when the transmitter is also stopped (both TX and RX
• Any ongoing receive transaction to the application (RX FIFO read) will continue
The status (and register bit) is cleared after the pause frame has been sent.
when the pause timer expired or a pause frame with zero quanta is received.
receive frames and hunt for magic packets if enabled (see
frames will be written into the receive FIFO and therefore will not be forwarded to the
application.
are stopped).
normally until the frame is completed (eop). After this, the following happens:
• When sleep mode is active, all further frames will be discarded, flushing the rx
FIFO.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SLEEP
SLEEP
or
or
SLEEP
SLEEP
bit (see
). The MAC will continue to
Sleep
Sleep
Mode). However, no
Freescale Semiconductor, Inc.
Mode).