MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1431

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Reset
WR_UNLOCK
RD_BANK_
SHADOWS
RELOAD_
Bit
W
RSRVD2
RSRVD1
RSRVD0
R
ERROR
31 16
15 14
OPEN
11 10
ADDR
BUSY
Field
7 6
5 0
13
12
9
8
15
RSRVD2
0
14
0
Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by-write
basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must contain the
correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be initiated. This field
is automatically cleared after a successful write completion (clearing of BUSY).
0x3E77
These bits always read back zero.
Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will automatically
open banks (but will not set RD_BANK_OPEN) and set BUSY. Once the shadow registers have been
re-loaded, BUSY and RELOAD_SHADOWS are automatically cleared by the controller. There is no need
to set RD_BANK_OPEN to force the reload. If RD_BANK_OPEN is already set, its still possible to set
RELOAD_SHADOWS. In this case, the shadow registers will only be updated upon the clearing of
RD_BANK_OPEN.
Set to open the all the OTP banks for reading. When set, the controller sets BUSY to allow time for the banks
to become available (approximately 32 HCLK cycles later at which time the controller will clear BUSY). Once
BUSY is clear, the various OTP words are accessible through their memory mapped address. Note that
OTP words which are shadowed, can be read at anytime and will not be affected by RD_BANK_OPEN. This
bit must be cleared after reading is complete. Keeping the OTP banks open causes additional current draw.
BUSY must be clear before this setting will take affect. If there is a write transaction pending (holding BUSY),
then the bank opening sequence will begin automatically upon the previous transaction clears BUSY. Note
that if a read is performed from non-shadowed locations without RD_BANK_OPEN, ERROR will be set
These bits always read back zero.
Set by the controller when either an access to a locked region is requested or a read is requested from
non-shadowed efuse locations without the banks being open. Must be cleared before any further write access
can be performed. This bit can only be set by the controller. This bit is also set if the Pin interface is active
and software requests an access to the OTP. In this instance, the ERROR bit cannot be cleared until the
Pin interface access has completed. Reset this bit by writing a one to the SCT clear address space and not
by a general write.
OTP controller status bit. When active, no new write access or bank open operations (including
RELOAD_SHADOWS) can be performed. Cleared by controller when access complete (for writes), or the
banks are open (for reads). After reset (or after setting RELOAD_SHADOWS), this bit is set by the controller
until the HW/SW and LOCK registers are successfully copied, after which time it is automatically cleared by
the controller.
These bits always read back zero.
OTP write access address register. Specifies one of 40 word address locations (0x00 - 0x27). If a valid write
is accepted by the controller (see HW_OCOTP_DATA for details on what constitutes a valid write), the
controller makes an internal copy of this value (to avoid the OTP programming being corrupted). This internal
copy will not update until the write access is complete.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
KEY — Key needed to unlock HW_OCOTP_DATA register.
12
0
HW_OCOTP_CTRL field descriptions
11
RSRVD1
0
10
0
0
9
BUSY
0
8
Description
RSRVD0
0
7
0
6
Chapter 20 On-Chip OTP (OCOTP) Controller
5
0
4
0
0
3
ADDR
0
2
0
1
1431
0
0