MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2248

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programming Example
37.3.9 Debugging Information
There are three read-only registers providing some useful information for debugging.
HW_HSADC_DBG_INFO0 provides HSADC_FSM_STATE , DMA_FSM_STATE and
DMA_REQ. The HSADC_FSM_STATE and DMA_FSM_STATE provides the state of
the FSMs inside the block, and the FIFO_READ_EMPTY can be used by ARM CPU for
polling the status of the FIFO. 1 means there is no data in the FIFO, 0 means there is data
in the FIFO. So, for some special user cases the ARM CPU can also read the data from the
asynchronous FIFO once there is data ready.
The HW_HSADC_DBG_INFO1 provides the sample count number of the current sequence
already finished. The HW_HSADC_DBG_INFO2 provides sequence count number already
finished.
37.3.10 Behavior During Reset
A soft reset (SFTRST) can take multiple clock cycles to complete, so do NOT set CLKGATE
when setting SFTRST. The reset process gates the clocks automatically.
37.4 Programming Example
The main target of this block is to drive the linear image scanner sensors, especially the
TOSHIBA TCD1304DG linear image scanner sensor. Let's take TOSHIBA TCD1304DG
linear image scanner sensor for example. Below is the steps to configure the
APBH-DMA,PWM and HSADC blocks:
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1. Configure the clock block to output clock to the analog ADC block. Then the analog
2. Clear the clock gating bits and soft reset bits for HSADC, PWM and APBH-DMA
3. Configure the HSADC block.Clear the POWER_DOWN bit in HSADC Control Register
ADC block will generate operation clock for the HSADC block and PWM block. The
frequency of the clock output to analog ADC block is 288MHz. Then the divider in
ADC block will divide the clock to 16x of the sample rate needed. For example, When
2Msps needed, the clock frequency output by the divider should be 32MHz.
block.
2. Assert the ADC_PRECHARGE bit in HSADC Control Register 2 so that the analog
ADC block can enter into a stable status and be ready for conversion. Once all the
parameters are set, set the hsadc_run bit in HSADC Control Register 0. Then the HSADC
block is in the state to wait the trigger pulse to start the conversion.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.