MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2032

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
32.2 Operation
The UTM provides a 16-bit interface to the USB controller. This interface is clocked at 30
MHz.
32.2.1 UTMI
The UTMI block handles the line_state bits, reset buffering, suspend distribution, transceiver
speed selection, and transceiver termination selection. The PLL supplies a 120 MHz signal
to all of the digital logic. The UTMI block does a final divide-by-four to develop the 30
MHz clock used in the interface.
32.2.2 Digital Transmitter
The digital transmitter receives the 16-bit transmit data from the USB controller and handles
the tx_valid, tx_validh and tx_ready handshake. In addition, it contains the transmit serializer
that converts the 16-bit parallel words at 30 MHz to a single bitstream at 480 Mbit for
high-speed or 12 Mbit for full-speed or 1.5 Mbit for low-speed. It does this while
implementing the bit-stuffing algorithm and the NRZI encoder that are used to remove the
DC component from the serial bitstream. The output of this encoder is sent to the low-speed
(LS), full-speed (FS) or high-speed (HS) drivers in the analog transceiver section's transmitter
block.
32.2.3 Digital Receiver
The digital receiver receives the raw serial bitstream from the low speed (LS) differential
transceiver, full speed (FS) differential transceiver, and a 9X, 480 MHz sampled data from
the high speed (HS) differential transceiver. As the phase of the USB host transmitter shifts
relative to the local PLL, the receiver section's HS DLL tracks these changes to give a
reliable sample of the incoming 480 Mbit/s bitstream. Since this sample point shifts relative
to the PLL phase used by the digital logic, a rate-matching elastic buffer is provided to cross
this clock domain boundary. Once the bitstream is in the local clock domain, an NRZI
decoder and bit unstuffer restore the original payload data bitstream and pass it to a
2032
• The digital portions of the USBPHY block include the UTMI, digital transmitter, digital
• The analog transceiver section comprises an analog receiver and an analog transmitter,
receiver, and the programmable registers.
as shown in
Figure
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
32-2.
Freescale Semiconductor, Inc.