MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1031

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.3.5 DCP Capability 1 Register (HW_DCP_CAPABILITY1)
This register contains information about the algorithms available on the implementation.
This register provides capability information for the DCP block. It contains two fields
indicating which encryption and hashing algorithms are present in the design. Each bit set
indicates that support for the associated function is present.
Address:
Re-
13.3.6 DCP Context Buffer Pointer (HW_DCP_CONTEXT)
This register contains a pointer to the memory region to be used for DCP context swap
operations.
This register contains a pointer to the start of the context pointer memory in on-chip SRAM
or off-chip SDRAM. This buffer will be used to store state information when the DCP
module changes from one channel to another.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
ALGORITHMS
ALGORITHMS
CIPHER_
31
31
0
0
HASH_
31 16
Field
15 0
30
30
0
0
29
29
0
0
HW_DCP_CAPABILITY1
HW_DCP_CONTEXT
28
28
0
0
One-hot field indicating which hashing features are implemented in HW.
0x0001
0x0002
0x0004
One-hot field indicating which cipher algorithms are available.
0x0001
27
27
0
0
HASH_ALGORITHMS
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
SHA1 —
CRC32 —
SHA256 —
AES128 —
24
24
0
0
HW_DCP_CAPABILITY1 field descriptions
23
23
0
0
22
22
0
0
8002_8000h base + 50h offset = 8002_8050h
8002_8000h base + 40h offset = 8002_8040h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
1
0
17
17
1
0
ADDR
16
16
1
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
CIPHER_ALGORITHMS
10
10
0
0
Chapter 13 Data Co-Processor (DCP)
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1031
1
0
0
0