MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1646

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

FIFO Thresholds
1646
RX_SECTION_EMPTY
RX_ALMOST_EMPTY
RX_SECTION_FULL
RX_ALMOST_FULL
Register
end-of-frame has not been received for the frame yet, the Core receive read control stops FIFO read
It continues to deliver the frame, if again more data than the threshold or the end-of-frame is available
When the FIFO level reaches the value programmed in the register RX_SECTION_EMPTY, an indic-
indication is provided to the MAC transmit logic, which generates a XON Pause frame to indicate the
internal signal. MAC will deassert the siganl again after asserted, if the fifo empties below the threshold
When programming a value>0 (cut-through operation) it should be greater than RX_ALMOST_EMPTY.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
When the FIFO level reaches the value programmed in the register RX_ALMOST_EMPTY, and the
ation is provided to the MAC transmit logic, which generates a XOFF Pause frame to indicate FIFO
When the FIFO level reaches the value programmed in the register RX_SECTION_FULL, the MAC
If a Frame has a size smaller than the threshold (i.e. an end-of-frame is available for the frame), the
will indicate uDMA that data is available in the Receive FIFO (cut-through operation) by asserted a
When the FIFO level goes below the value programmed in the register RX_SECTION_EMPTY, an
To enable store and forward on the receive path, set the register RX_SECTION_FULL to 0. In this
RX_ALMOST_FULL number of words, the MAC control logic stops writing data in the FIFO and
set with RX_ALMOST_EMPTY, and if the end-of-frame is not yet stored in the fifo (Hysteresis).
Table 26-23. Receive FIFO Thresholds Definition
When the FIFO level comes close to the maximum, so that there is no more space for at least
The corresponding error status will be set when the frame is delivered to the application.
case, The signal is asserted only when a complete frame is stored in the receive FIFO.
Figure 26-21. Receive FIFO Overview
(and subsequently stops transferring data to the MAC client application).
FIFO congestion is cleared to the remote Ethernet client.
truncates the received frame to avoid FIFO overflow.
A value of 0 disables any pause frame generation.
congestion to the remote Ethernet client.
A minimum value of 6 should be set.
A minimum value of 4 should be set.
status is also asserted.
(Pause Frame Generation)
Description
in the FIFO.
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