MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 854

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chip Reset
The requirement is that the roots of the clock are configured and stable before the elements
higher up in the tree are programmed. This will allow the roots to stabilize before selected
as a valid source to drive a clock trunk/tree. If this sequence is not honored, unpredictable
frequencies can occur which may violate the maximum operating frequency of components
on the respective clock trees. Be sure to gate off the clock paths directly downstream from
the PLL before powering off the PLL.
When clk_emi is operating in synchronous mode, the following requirements must be
maintained:
10.7 Chip Reset
Two PIO accessible soft reset bits exists to establish the initial state of the device. These
bits are called HW_CLKCTRL_RESET_CHIP and HW_CLKCTRL_RESET_DIG. Setting
these bits will result in a chip wide reset cycle. When setting the DIG software reset bit, the
digital logic is reset with the exception of the power module and the DCDC converter control
logic. The CHIP software reset bit also initiates the full reset cycle and the power and the
DCDC converter logic are also reset. These two soft reset bits themselves reset during a
soft reset sequence.
Ethernet module is a special case. To avoid network traffic blocking, Ethernet Switch need
to maintain working as long as possible. So when the Ethernet module is in Switch mode,
it can be configured to only POR resettable by setting both
HW_CLKCTRL_ENET_RESET_BY_SW_CHIP and
HW_CLKCTRL_ENET_RESET_BY_SW to 0. If Ethernet module is not in Switch mode,
it will be reset by both DIG software reset bit and CHIP reset bit regardless of the value of
HW_CLKCTRL_ENET_RESET_BY_SW_CHIP and
HW_CLKCTRL_ENET_RESET_BY_SW.
The following figure shows the functionality of these two reset bits.
854
7. Switch the bypass to off (select PLL, not crystal).
• The clk_p divide value is less than or equal to the clk_emi divide value.
• The clk_emi divide value must be divisable by the clk_p divide value. An example of
possible clk_p:clk_emi divide values would be, but not limited, to 1:1, 1:2, 1:3, 2:2,
2:4, 2:6, 3:3, 3:6, 3:9.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.