MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1779

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 28 Pulse-Width Modulator (PWM) Controller
Figure 28-5
shows the generation of the PWM Channel 3 output. This channel controls the
output pin when PWM control is selected in PINCTRL block and
HW_PWM_CTRL_PWM3_ENABLE is set to 1. The output pin can be set to a 0, a 1, or
left to float in the high-impedance state. These choices can be made independently for either
the active or inactive phase of the output.
28.2.2 HSADC Driving Mode
The HSADC driving mode ouputs signals in HSADC (high-speed ADC) sample clock
domain, other than traditional 24 MHz XTAL OSC domain.
Although the main target of HSADC block is to drive TOSHIBA TCD1304DG linear image
scanner sensor, there is potential requirement for HSADC to drive other linear image scanner
sensors as well. To improve flexibility, PWM is used to generate these driving signals; and
to co-work with block HSADC, HSADC's sample clock is used for PWM output signals.
Typically, as which is showed in
Figure
28-4, three output driving signals are needed for
HSADC. And one extra trigger, which is also synchronous with high-speed ADC block,
might be needed to start the conversion of ADC according to HSADC's specified trigger
mode.
As a result, one clock mux is added for every PWM instance each to output signals
synchronous with HSADC sample clock, and there is a hard-wired connection between
every PWM instance and high-speed ADC block for HSADC's PWM trigger mode.
For every PWM instance, software can choose whether HSADC sample clock or 24 MHz
XTAL OSC clock is used for PWM output by writing 1'b1 to bit HSADC_CLK_SEL of
Register PWM Channelx Period Register(x = 0-7). Meanwhile, it's programmable whether
this output signal is routed to HSADC internally by writing 1'b1 to bit HSADC_OUT of
Register PWM Channelx Period Register(x = 0-7). When on HSADC driving mode, it is
advisable to wait enough time for another write access to the same PWM register, such as
HW_PWM_CTR, HW_PWM_ACTIVEx(x = 0-7) and HW_PWM_PERIODx(x = 0-7).
Because handshake is applied, if several write access to the same register is consecutive to
each other, it is not guaranteed what's the content of programmed register.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1779