MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1124

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
14.8.19 DRAM Control Register 21 (HW_DRAM_CTL21)
This is a DRAM configuration register.
Address:
1124
Reset
SREFRESH
SREFRESH
ENABLE_
Bit
W
R
QUICK_
RSVD1
Field
7 1
8
0
31
0
HW_DRAM_CTL21
30
0
Allow user to interrupt memory initialization to enter self-refresh mode.
When this bit is set to 'b1, the memory initialization sequence may be interrupted and the memory may enter
self-refresh mode. This is used to place the memory devices into self-refresh mode when a power loss is
detected during the initialization process.
'b0 = Continue memory initialization.
'b1 = Interrupt memory initialization and enter self-refresh mode.
Always write zeroes to this field.
Place DRAMs in self-refresh mode.
When this parameter is set to 'b1, the DRAM device(s) will be placed in self-refresh mode. For this, the
current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh
command will be issued to the DRAM, and the clock enable signal will be de-asserted. The system will
remain in self-refresh mode until this parameter is cleared to 'b0. The DRAM devices will return to normal
operating mode after the self-refresh exit time (the txsr parameter) of the device and any DLL initialization
time for the DRAM is reached. The EMI will resume processing of the commands from the interruption point.
This parameter will be updated with an assertion of the srefresh_enter pin, regardless of the behavior on
the register interface. To disable self-refresh again after a srefresh_enter pin assertion, the user will need
to clear the parameter to 'b0.
'b0 = Disable self-refresh mode.
'b1 = Initiate self-refresh of the DRAM devices.
RSVD3
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DRAM_CTL17 field descriptions (continued)
28
0
800E_0000h base + 54h offset = 800E_0054h
27
0
26
0
CKE_DELAY
25
0
24
0
Description
23
0
22
0
21
0
DLL_LOCK
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0