MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1428

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Behavior During Reset
20.3 Behavior During Reset
The OCOTP is always active. The shadow registers described in
automatically load the appropriate OTP contents after reset is deasserted. During this
load-time HW_OCOTP_CTRL_BUSY is set. The load time is approximately 32 HCLK
cycles after the deassertion of reset. These shadow registers can be reloaded as described
in
20.4 Programmable Registers
OCOTP Hardware Register Format Summary
1428
8002_C0A0
8002_C0B0
8002_C0C0
8002_C0D0
8002_C0E0
8002_C000
8002_C010
8002_C020
8002_C030
8002_C040
8002_C050
8002_C060
8002_C070
8002_C080
8002_C090
8002_C0F0
8002_C100
Absolute
address
Shadow Registers and Hardware Capability
(hex)
OTP Controller Control Register (HW_OCOTP_CTRL)
OTP Controller Write Data Register (HW_OCOTP_DATA)
Value of OTP Bank0 Word0 (Customer)
(HW_OCOTP_CUST0)
Value of OTP Bank0 Word1 (Customer)
(HW_OCOTP_CUST1)
Value of OTP Bank0 Word2 (Customer)
(HW_OCOTP_CUST2)
Value of OTP Bank0 Word3 (Customer)
(HW_OCOTP_CUST3)
Value of OTP Bank0 Word4 (Crypto Key)
(HW_OCOTP_CRYPTO0)
Value of OTP Bank0 Word5 (Crypto Key)
(HW_OCOTP_CRYPTO1)
Value of OTP Bank0 Word6 (Crypto Key)
(HW_OCOTP_CRYPTO2)
Value of OTP Bank0 Word7 (Crypto Key)
(HW_OCOTP_CRYPTO3)
HW Capability Shadow Register 0 (HW_OCOTP_HWCAP0)
HW Capability Shadow Register 1 (HW_OCOTP_HWCAP1)
HW Capability Shadow Register 2 (HW_OCOTP_HWCAP2)
HW Capability Shadow Register 3 (HW_OCOTP_HWCAP3)
HW Capability Shadow Register 4 (HW_OCOTP_HWCAP4)
HW Capability Shadow Register 5 (HW_OCOTP_HWCAP5)
SW Capability Shadow Register (HW_OCOTP_SWCAP)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_OCOTP memory map
Bus.
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Programmable Registers
R
R
R
R
R
R
R
R
Freescale Semiconductor, Inc.
Reset value
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
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