MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1580

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
25.6.2 Control Register (HW_CAN_CTRL)
This register is defined for specific CAN control features related to the CAN bus. The default
value of this register is 0x00000000.
This register is defined for specific FlexCAN control features related to the CAN bus, such
as bit rate, programmable sampling point within an Rx bit, loopback mode, listen-only
mode, bus-off recovery behavior and interrupt enabling (bus-off, error, warning). It also
determines the division factor for the clock prescaler. Most of the fields in this register can
only be changed while the module is in disable mode or in freeze mode. Exceptions are the
BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK and BOFF_REC bits, that can be
accessed at any time.
Address:
1580
Reset
LPRIO_EN
Bit
W
R
MAXMB
RSVD2
RSVD1
RSVD0
15 14
11 10
IDAM
Field
AEN
9 8
7 6
5 0
13
12
31
0
HW_CAN_CTRL
30
0
Reserved.
This bit is provided for backwards compatibility reasons. It controls whether the local priority feature is
enabled or not.
This bit is supplied for backwards compatibility reasons.
Reserved.
This 2-bit field identifies the format of the elements of the Rx FIFO filter table
Reserved.
This 6-bit field defines the maximum number of message buffers that will take part in the matching and
arbitration processes.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CAN_MCR field descriptions (continued)
PRESDIV
28
0
8003_2000h base + 4h offset = 8003_2004h
27
0
26
0
25
0
24
0
Description
23
0
RJW
22
0
21
0
PSEG1
20
0
Freescale Semiconductor, Inc.
19
0
18
0
PSEG2
17
0
16
0