MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1598

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Unified DMA Block Guide
26.2.2.1.1.7
in promiscuous mode, but flagged as a miss by the internal address recognition. Therefore,
while in promiscuous mode, the user can use the M-bit to quickly determine whether the
frame was destined to this station. This bit is only valid if the L-bit is set and the PROM
bit is set inside the ENET-MAC. If 0,the frame was received because of an address
recognition hit. If 1, the frame was received because of promiscuous mode. This field is
only valid if the BD is the last in the frame, that is, L-bit is set.
26.2.2.1.1.8
26.2.2.1.1.9
26.2.2.1.1.10
than MAX_FL was recognized. This bit is valid only if the L-bit is set. The receive data is
not altered in any way unless the length exceeds TRUNC_FL bytes.
26.2.2.1.1.11
contained a number of bits not divisible by 8 was received, and the CRC check that occurred
at the preceding byte boundary generated an error or Phy error occurred. This bit is valid
only if the L-bit is set. If this bit is set the CR bit will not be set.
26.2.2.1.1.12
26.2.2.1.1.13
Frame with Phy error or CRC error and is an integral number of octets in length. This bit
is valid only if the L-bit is set.
26.2.2.1.1.14
frame reception. If this bit is set, the other status bits, M, LG, NO, SH, CR, and CL lose
their normal meaning and will be zero. This bit is valid only if the L-bit is set.
26.2.2.1.1.15
If the TR bit is set, the frame should be discarded and the other error bits should be ignored
as they may be incorrect.
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Bit-8 M
Miss. Written by the uDMA. This bit is set by the uDMA for frames accepted
Bit-7 BC
Set if the DA is broadcast (FF-FF-FF-FF-FF-FF).
Bit-6 MC
Set if the DA is multicast and not BC.
Bit-5 LG
Rx frame length violation, written by the uDMA. A frame length greater
Bit-4 NO
Receive non-octet aligned frame, written by the uDMA. A frame that
Bit-3
Reserved.
Bit-2 CR
Rx CRC or Rx Frame error, written by the uDMA. This frame contains a
Bit-1 OV
Overrun, written by the uDMA. A receive FIFO overrun occurred during
Bit-0 TR
Will be set if the receive frame is truncated (frame length > TRUNC_FL).
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.