MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1168

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
14.8.67 DRAM Control Register 72 (HW_DRAM_CTL72)
This is a DRAM configuration register.
Address:
Re-
1168
set
Bit
W
R
31
0
Field
30
0
29
0
HW_DRAM_CTL72
28
0
'b1 = Enabled
Bits [26:24] = Defines the read data delay. Holds the number of cycles to delay the dfi_rddata_en signal
prior to enabling the read FIFO. After this delay, the read pointers begin incrementing the read FIFO. Default
0x3.
Bit [20] = Sets the pad output enable polarity. Default 0x0.
'b0 = OEN pad
'b1 = OE pad
Bit [16] = Subtracts 1/2 cycle from the DQS gate value programmed into phy_ctrl_reg_1_X [2:0] by 1/2 cycle.
Default 0x0. This is used when the gate is being aligned to the first DQS, and then is removed to move the
gate back into the center of the preamble. This parameter is controlled by the hardware logic when hardware
gate training is enabled but should be controlled by software when software leveling is used.
'b0 = Do not adjust
'b1 = Adjust the DQS gate by 1/2 clock forward.
Bits [15:12] = Adjusts the starting point of the DQS pad output enable window. Lower numbers pull the rising
edge earlier in time, and larger numbers cause the rising edge to be delayed. Each bit changes the output
enable time by a 1/4 cycle resolution. Default 0x2.
Bits [11:8] = Adjusts the ending point of the DQS pad output enable window. Lower numbers pull the falling
edge earlier in time, and larger numbers cause the falling edge to be delayed. Each bit changes the output
enable time by a 1/4 cycle resolution. Default 0x7.
Bits [6:4] = Adjusts the starting point of the DQ pad output enable window. Lower numbers pull the rising
edge earlier in time, and larger numbers cause the rising edge to be delayed. Each bit changes the output
enable time by a 1/4 cycle resolution. Default 0x1.
Bits [2:0] = Adjusts the ending point of the DQ pad output enable window. Lower numbers pull the falling
edge earlier in time, and larger numbers cause the falling edge to be delayed. Each bit changes the output
enable time by a 1/4 cycle resolution. Default 0x4.
All other bits undefined.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL71 field descriptions (continued)
24
0
23
0
800E_0000h base + 120h offset = 800E_0120h
22
0
21
0
20
0
19
0
PHY_CTRL_REG_0_1
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0