MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 502

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

APBX DMA
Figure 7-3
bit is set to 1, if the NEXT_COMMAND_ADDRESS contains a pointer to another DMA
command structure. If a null pointer (0) is loaded into the NEXT_COMMAND_ADDRESS,
it will not be detected by the DMA hardware. Only the CHAIN bit indicates whether a valid
list exists beyond the current structure.
If the IRQ_COMPLETE bit is set in the command structure, then the last act of the DMA
before loading the next command is to set the interrupt status bit corresponding to the current
channel. The sticky interrupt request bit in the DMA CSR remains set until cleared by the
software. It can be used to interrupt the CPU.
Each channel has an eight-bit counting semaphore that controls whether it is in the run or
idle state. When the semaphore is non-zero, the channel is ready to run and process
commands and DMA transfers. Whenever a command finishes its DMA transfer, it checks
the DECREMENT_SEMAPHORE bit. If set, it decrements the counting semaphore. If the
semaphore goes to 0 as a result, then the channel enters the IDLE state and remains there
until the semaphore is incremented by software. When the semaphore goes to non-zero and
the channel is in its IDLE state, then it uses the value in the HW_APBX_CHn_NXTCMDAR
(next command address register) to fetch a pointer to the next command to process. NOTE:
this is a double indirect case. This method allows software to append to a running command
list under the protection of the counting semaphore.
Receiving an IRQ for HALTONTERMINATE (HOT) is a new feature in the APBH/X
DMA descriptor that allows certain peripheral block (for example, GPMI, SSP, I2C) to
signal to the DMA engine that an error has occurred. In prior chips, if a block stalled due
to an error, the only practical way to discover this in software was through a timer of some
sort, or to poll the block. Now, an HOT signal is sent from the peripheral to the DMA engine
and causes an IRQ after terminating the DMA descriptor being executed. Note not all
peripheral block support this termination feature.
502
31
30
Zero or More PIO Words to Write to the Associated Peripheral Starting at its Base Address on the APBX Bus
29
28
shows the CHAIN bit in bit 2 of the second word of the command structure. This
Number DMA Bytes to Transfer
27
26
25
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
24
23
22
21
20
DMA Buffer or Alternate CCW
19
18
17
16
15
Number PIO
Words to
14
Write
13
12
11
10
09
08
07
Freescale Semiconductor, Inc.
06
05
04
03
02
01
00