MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1276

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programming the BCH/GPMI Interfaces
// Descriptor 9: emit GPMI interrupt
//----------------------------------------------------------------------------
write[8].dma_nxtcmdar = NULL;
descriptor
write[8].dma_cmd = BF_APBH_CHn_CMD_XFER_COUNT
16.4.1.2 Using the BCH Encoder
To use the BCH encoder, first turn off the module-wide soft reset bit in both the GPMI and
BCH blocks before starting any DMA activity. Turning off the soft reset must take place
by itself, prior to programming the rest of the control registers. Turn off the BCH bus master
soft reset bit (bit 29). Turn off the clock gate bits.
Program the remainder of the GPMI, BCH and APBH DMA as follows:
Note that for writing NANDs (ECC encoding), only GPMI DMA command complete
interrupts are used. The BCH engine is used for writing to the NAND but may optionally
produces an interrupt. From the sample code in
1276
• DMA descriptor 1 prepares the NAND for data write by using the GPMI to issue a
write setup command byte under CLE, then sends a 5-byte address under ALE. The
BCH engine is disabled and not used for these commands.
// bring APBH out of reset
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_SFRST);
HW_APBH_CTRL0_CLR(BM_APBH_CTRL0_CLKGATE);
// bring BCH out of reset
HW_BCH_CTRL_CLR(BM_BCH_CTRL_SFTRST);
HW_BCH_CTRL_CLR(BM_BCH_CTRL_CLKGATE);
// bring gpmi out of reset
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_SFTRST);
HW_GPMI_CTRL0_CLR(BM_GPMI_CTRL0_CLKGATE);
HW_GPMI_CTRL1_SET(BM_GPMI_CTRL1_DEV_RESET | // deassert reset
// enable pinctrl
HW_PINCTRL_CTRL_WR(0x00000000);
// enable GPMI through alt pin wiring
HW_PINCTRL_MUXSEL0_CLR(0xff000000);
HW_PINCTRL_MUXSEL0_SET(0xaa000000);
// to use the primary pins do the following
//
//
// enable gpmi pins
HW_PINCTRL_MUXSEL0_CLR(0x0000ffff); // data bits
HW_PINCTRL_MUXSEL1_CLR(0x000fffff); // control bits
HW_PINCTRL_MUXSEL4_CLR(0xff000000);
HW_PINCTRL_MUXSEL4_SET(0x55000000);
BF_APBH_CHn_CMD_CHAIN
BF_APBH_CHn_CMD_CMDWORDS
BF_APBH_CHn_CMD_WAIT4ENDCMD
BF_APBH_CHn_CMD_SEMAPHORE
BF_APBH_CHn_CMD_NANDWAIT4READY(0)
BF_APBH_CHn_CMD_NANDLOCK
BF_APBH_CHn_CMD_IRQONCMPLT
BV_FLD(APBH_CHn_CMD, COMMAND, NO_DMA_XFER);
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
BM_GPMI_CTRL1_BCH_MODE
); // enable BCH mode
(0)
(0)
(0)
(0)
(0)
(0)
(1)
DMA Structure Code
| // terminate DMA chain processing
| // no dma transfer
| // no words sent to GPMI
| // do not wait to continue
|
|
|
| // emit GPMI interrupt
// not used since this is last
// no dma transfer
Freescale Semiconductor, Inc.
Example: