MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1076

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

EMI AHB and AXI Interface
14.4.8.7 Passing Exclusive Access Check
If any of the valid buffer entries exactly match the incoming command, the following
activities occur:
14.4.8.8 Failing Exclusive Access Check
If an invalid buffer entry exactly matches the incoming command, or no buffer entries
exactly match the incoming command, then the write will fail. The command will be
processed internally as a flushed write command.
For a flushed write, the write data will be cleared out of the memory controller FIFOs but
the data stored in external DRAM memory will NOT change.
The user will be informed of this condition through the write response channel (axi_BRESP).
However, instead of an EXOKAY response, the memory controller will issue an OKAY
response. This indicates to the master that the exclusive write did not occur. The master
may re-issue the request as a non-exclusive write, or may restart the process by re-issuing
the exclusive read.
14.4.9 Error Responses
This section discusses AXI error responses and AXI error reporting.
14.4.9.1 AXI Error Response
When an illegal operational condition is detected on a new AXI transaction entering the
port, the port responds with an error condition. Instructions that generate AXI errors result
in unpredictable behavior and may cause memory corruption and/or hang conditions.
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• That buffer entry's “valid” bit is cleared.
• All other buffer entries, from this port or other ports, are checked to see if this write
• The transaction is processed.
• If successful, the write response channel (axi_BRESP) returns an EXOKAY response
invalidates any other exclusive access regions. If so, the “valid” bits of these entries
will be cleared.
(‘b01) to the master.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.