MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 134

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
The FSM reverts to its BASE level state waiting for an interrupt request to arrive in the
holding register. The waveform for the IRQ mask in the CPU status register (CSR) and the
waveform for the IRQ input to the CPU as they relate to the interrupt collector action are
shown in
5.2.2 FIQ Generation
On this device, all interrupt sources can be configured as FIQ. This is controlled through
the HW_ICOLL_INTERRUPTn[ENFIQ] register bit as shown in
to the FIQ, the software interrupt associated with these bits can be used to generate the FIQ
from these sources for test purposes. When an interrupt source is programmed as an FIQ,
and IRQ cannot be generated from that source.
5.2.3 Interrupt Sources
The following table lists all of the interrupt sources on the device. Use hw_irq.h to access
these bits.
134
Number
Source
0
batt_brownout_irq
Figure
Interrupt
There is an inherent race condition between notifying the interrupt
collector that an ISR has been entered and having that ISR
re-enable IRQ exceptions in the CSR. The in-service notification
can take a number of cycles to percolate through the write buffer,
through the AHB and APB bridge and into the interrupt collector
where it removes the IRQ assertion to the CPU. This ICOLL IRQ
must be deasserted before the CSR IRQ on the CPU is re-enabled
or the CPU will see a phantom interrupt. This is why the ARM
vectored interrupt controller provides this in-service notification
as a read side effect of the vector address read. Alternatively, the
ISR can read the interrupt collector's CSR. The value received is
unimportant, but the time required to do the read ensures that the
write data has arrived at the interrupt collector. If firmware uses
this method, it should allow clocks after the read for the FSM and
for the CPU to recognize that the IRQ has been deasserted.
5-4.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 5-1. i.MX28 Interrupt Sources
0x0000
Vector
NOTE
Power module battery brownout detect IRQ, recom-
mend to set as FIQ.
Description
Figure
Freescale Semiconductor, Inc.
5-2. When enabled