MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 117

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3
Default First-level Page Table (DFLPT)
3.1 Default First-Level Page Table (DFLPT) Overview
The DFLPT provides a unique method of implementing the ARM MMU first-level page
table (L1PT) using a hardware-based approach. The ARM MMU L1PT must consist of
4096 page-table entries (PTE), each of which maps to a 1-Mbyte section of the 4-Gbyte
system memory. Each PTE consists of a 32-bit descriptor, such that 16 Kbytes of memory
is required to implement the L1PT. Using 16 Kbytes of system memory for the L1PT can
be an issue for memory-constrained embedded systems (especially those without SDRAM).
The DFLPT implements a very sparse L1PT in hardware, as shown in
achieved by having sixteen movable and expandable page table entries (MPTE) that are
fully programmable and one semi-programmable fixed PTE. Any of the sixteen MPTEs
can be bound to 4095 of the 4096 sections using sixteen locator registers in the DIGCTL
block (MPTE0_LOC).
This implementation, although sparse, is very useful in low-memory applications. For small
SDRAM systems (where the L1PT would typically be placed in SDRAM), the DFLPT
provides significant speed and power advantages (as well as saving 16 Kbytes). For larger
DRAM system, it provides a performance advantage. Large memory systems are
accommodated through the spanning option (for example, in cases such as multimedia
buffers, large amounts of memory are typically marked with the same attributes, and the
memory is contiguous physically). Using the DFLPT, a level-one descriptor fetch takes two
HCLK cycles to complete.
Freescale Semiconductor, Inc.
Figure 3-1. Default First-Level Page Table (DFLPT) Block Diagram
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
OCROM
OCROM
USB
USB
Slave
Slave
Slave
Slave
Page Table
Page Table
First-Level
First-Level
Default
Default
ARM Core
ARM Core
Slave
Slave
Data Master
Data Master
AHB Layer 2
AHB Layer 2
Bridge
Bridge
APBH
APBH
Slave
Slave
OCRAM
OCRAM
Bridge
Bridge
APBX
APBX
Slave
Slave
Slave
Slave
EMI
EMI
Slave
Slave
Figure
3-1. This is
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