MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1759

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
RD_QUEUE_IRQ
ADDRESS_BYTE
BCAST_SLAVE_
CMPLT_IRQ_EN
DATA_ENGINE_
FORCE_DATA_
FORCE_CLK_
CLR_GOT_A_
WR_QUEUE_
ACK_IRQ_EN
BUS_FREE_
NO_SLAVE_
ACK_MODE
IRQ_EN
SLAVE_
RSVD1
23 16
Field
IDLE
IDLE
NAK
IRQ
EN
31
30
29
28
27
26
25
24
15
14
13
Always set this bit field to zero.
This bit is set to indicate that an interrupt is requested by the I2C controller because the read queue threshold
criterion has been met. This bit is cleared by software by writing a one to its SCT clear address. Note that
the enable bit for this interrupt is in the HW_I2C_QUEUECTRL register.
0x0
0x1
This bit is set to indicate that an interrupt is requested by the I2C controller because the write queue threshold
criterion has been met. This bit is cleared by software by writing a one to its SCT clear address. Note that
the enable bit for this interrupt is in the HW_I2C_QUEUECTRL register.
0x0
0x1
Setting this bit will clear the got_a_nak.
0x0
0x1
This setting affects the behavior of the ACK pulse when RETAIN_CLOCK=1.
0x0
0x1
Writing a one to this bit will force the data state machine to return to its idle state and stay there.
Writing a one to this bit will force the clock generator state machine to return to its idle state and stay there.
Set this bit to one to enable the slave address search machine to look for both a match to the programmed
slave address as well as a match to the broadcast address of all zeroes.
0x0
0x1
Slave address byte, note the slave address is only seven bits long. The slave address search state machine
will respond to either a read or a write command issued to the seven bit address. Set the LSB (bit 0) to one
to match ALL 7 bit i2c addresses.
Set this bit to one to enable bus free interrupt requests to be routed to the interrupt collector. Set to zero to
disable interrupts from the I2C controller.
0x0
0x1
Set this bit to one to enable data engine complete interrupt requests to be routed to the interrupt collector.
Set to zero to disable interrupts from the I2C controller.
0x0
0x1
Set this bit to one to enable interrupt requests to be routed to the interrupt collector. Set to zero to disable
interrupts from the I2C controller.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
NO_REQUEST — No Interrupt Request Pending.
REQUEST — Interrupt Request Pending.
DO_NOTHING —
CLEAR — Clear got_a_nak.
ACK_AFTER_HOLD_LOW — ACK will occur after clock is held low at start of next access.
ACK_BEFORE_HOLD_LOW — ACK will occur at end of access before clock is held low.
NO_BCAST — Do not watch for broadcast address while matching programmed slave address.
WATCH_BCAST — Watch for the all zeroes broadcast address while matching programmed slave
address.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
DISABLED — No Interrupt Request Pending.
ENABLED — Interrupt Request Pending.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_I2C_CTRL1 field descriptions
Description
Chapter 27 Inter IC (I2C)
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