MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1204
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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Programmable Registers
14.8.127 DRAM Control Register 132 (HW_DRAM_CTL132)
This is a DRAM configuration register.
Address:
Re-
14.8.128 DRAM Control Register 133 (HW_DRAM_CTL133)
This is a DRAM configuration register.
Address:
Re-
1204
set
set
DLL_OBS_REG_
Bit
DLL_OBS_REG_
Bit
W
W
R
R
OBSOLETE
31
31
0
0
RSVD1
31 16
31 0
15 9
Field
Field
2_1
8 0
2_1
30
30
0
0
29
29
0
0
HW_DRAM_CTL132
HW_DRAM_CTL133
28
28
0
0
Reports the read DQS delay value for data slice 1. READ-ONLY.
Always write zeroes to this field.
Always write zeroes to this field.
Reports the read DQS delay value for data slice 1. READ-ONLY.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
OBSOLETE
24
24
0
0
23
23
0
0
HW_DRAM_CTL131 field descriptions
HW_DRAM_CTL132 field descriptions
800E_0000h base + 210h offset = 800E_0210h
800E_0000h base + 214h offset = 800E_0214h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
DLL_OBS_REG_2_2
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
RSVD1
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
DLL_OBS_REG_2_1
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0
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