MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1669

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.4.9 ENET MAC Receive Control Register (HW_ENET_MAC_RCR)
Address:
Freescale Semiconductor, Inc.
Reset
Reset
MIB_CLEAR
NO_LGTH_
MIB_IDLE
Bit
Bit
W
W
MIB_DIS
RSRVD0
MAX_FL
R
R
CHECK
29 16
Field
28 0
Field
GRS
31
30
29
31
30
GRS
31
15
0
0
HW_ENET_MAC_RCR
CRC_
FWD
30
14
0
0
A read/write control bit. If set, the MIB logic halts and does not update any MIB counters.
A read-only status bit. If set the MIB block is not currently updating any MIB counters.
A read/write control bit. If set all statistics counters are reset to 0.
Reserved bits. Write as 0.
Graceful receive stopped. Read-only status indicating that the MAC receive datapath is stopped
Payload Length Check Disable. When set to 1, the controller checks the frame's payload length with the
Frame Length/Type field. When set to 0 (Reset value) the payload length check is disabled
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC
at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt to occur. Receive
frames longer than MAX_FL causes the BABR interrupt to occur and sets the LG bit in the end of frame
receive buffer descriptor. Set to 1518 (Decimal) after reset.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
PAD_
EN
28
12
0
0
HW_ENET_MAC_MIBC field descriptions
HW_ENET_MAC_RCR field descriptions
27
11
0
0
800F_0000h base + 84h offset = 800F_0084h
26
10
1
0
25
0
0
9
24
1
0
8
Description
Description
23
MAX_FL
1
0
7
22
1
0
6
FCE
21
1
5
0
Chapter 26 Ethernet Controller (ENET)
BC_
REJ
20
0
4
0
19
1
0
3
18
1
0
2
DRT
17
1
0
1
1669
16
0
1
0