MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1070

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

EMI AHB and AXI Interface
14.4.3 Port Clocking
There are four user-selectable modes of operation for each of the AXI port interfaces. The
mode is set by programming the corresponding axiY_fifo_type_reg parameter. The four
settings are:
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• Exclusive Access Buffer Depth
• Error Detection
• Synchronous (‘b11)
• 1:2 Port:Core Pseudo-Synchronous (‘b10)
Exclusive access is an optional AXI feature that is only supported for the native AXI
ports. This type of access will only be used if exclusive access commands are issued
to the memory controller by driving the axiY_ARLOCK signal to ‘b10 with a read
command.
Each native AXI port contains 1 exclusive buffer and therefore each port may monitor
the exclusivity of up to 1 transaction at any time. Refer to section
more information.
When an illegal operational condition is detected on a new AXI transaction entering
the port, the port responds through an AXI error signal and the controller interrupt
signal, and the error signature is recorded in the register space.
The AXI error signal flagged is dependent on the type of transaction that caused the
error (read or write). The controller interrupt and the signature information is dependent
on type of error (command or data). Refer to section
information on error detection.
The AXI port clock and the emi_clk must be aligned in frequency in phase. The AXI
port interface block will not be required to perform any clock synchronization in any
of the FIFOs.
Reserved. Do not select this mode. Select “Asynchronous” instead.
Port Num-
ber
Port
3
Port Data
Width
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
32
Clock Domain Type
Programmable
FIFO Depth
Command
4
Write FIFO
Depth
Error Responses
8
Read FIFO
Depth
8
Freescale Semiconductor, Inc.
Exclusive Access
FIFO Depth
Response
for more
4
Storage Ar-
Response
ray Depth
8
for