MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1426

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
It should be noted that write latencies to OTP are in the order of 10s to 100s of microseconds
per word. Write latencies will vary based on the location of the word within the OTP bank.
Once a write is initiated, HW_OCOTP_DATA is shifted one bit per every 32 HCLK cycles.
Given:
Then, the approximate write latency for a given word is:
In addition to this latency, software must allow for the 2-μs postamble (using
HW_DIGCTL_MICROSECONDS), as described in
20.2.3 Write Postamble
Due to internal electrical characteristics of the OTP during writes, all OTP operations
following a write must be separated by 2 μs after the clearing of HW_OCOTP_CTRL_BUSY
following the write. This guarantees programming voltages on-chip to reach a steady state
when exiting a write sequence. This includes reads, shadow reloads, or other writes. A
recommended software sequence to meet the postamble requirements is as follows:
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6. Once complete, the controller clears BUSY. Beyond this, the 2-μs postamble requirement
1. Issue the write and poll for BUSY (as per
2. Once BUSY is clear, use HW_DIGCTL_MICROSECONDS to wait 2 μs.
3. Perform the next OTP operation.
HW_OCOTP_CTRL_ADDR that cannot be updated until the next write sequence is
initiated. This copy guarantees that erroneous writes to HW_OCOTP_CTRL_ADDR
will not affect an active write operation. It should also be noted that, during
programming, HW_OCOTP_DATA will shift right (with zero fill). This shifting is
required to program the OTP serially. During the write operation, HW_OCOTP_DATA
cannot be modified.
must be met before submitting any further OTP operations (see
write request to a protected region will result in no OTP access and no setting of
HW_OCOTP_CTRL_BUSY. In addition, HW_OCOTP_CTRL_ERROR will be set.
It must be cleared by software before any new write access can be issued.
8 words per OTP bank
32 bits per word
tHCLK is the HCLK clock period
n word locations (where 0 n 7)
tHCLK * 32 * 32 * n
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Software Write
Write Postamble
Sequence).
Write
Freescale Semiconductor, Inc.
Postamble). A