MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1735
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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To receive one data byte from a slave device such as an FM tuner, the following bus
transaction takes place.
In this transaction:
The following example shows a multiple byte read from an FM tuner or other slave device:
27.2.2.2 Typical EEPROM Transactions
I
bytes to and from the EEPROM array.
bytes of data as a sub-address for purposes of illustration. The sub-address is used to address
the memory space inside the device.
shown. When writing a single byte of data to the EEPROM, one must first transfer two
bytes of sub-address as follows:
Freescale Semiconductor, Inc.
2
C EEPROMs typically have a specific transaction sequence for reading and writing data
• The master first generates a start condition, ST.
• It then sends the seven-bit slave address for the FM tuner plus a read bit (SAD+R).
• The slave in the FM tuner responds with a slave acknowledge bit (SAK).
• The master then generates I
• The slave provides data to the I
• Next, the master generates a master non-acknowledge to the slave (NMAK), indicating
• Finally, the master generates a stop condition (SP), terminating the transaction and
ST
the end of the data transfer to the slave. The slave will then release the data line.
freeing the I
ST
NMAK
MAK
BIT
SP
SAD+R
2
C bus for other masters to use.
Table 27-5. I
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 27-4. I
SAK
Stop Condition
Master Acknowledge
No Master Acknowledge
Description
SAD+R
DATA
2
C Transfer FM Tuner Read of Three Bytes
2
2
C Transfer FM Tuner Read of One Byte
C clocks for a data byte to be transferred (DATA).
2
C data bus during the DATA byte transfer.
Table 27-3
MAK
Table 27-6
SAK
DATA
defines each element of the transactions
through
MAK
Table 27-9
DATA
DATA
show the first two
Chapter 27 Inter IC (I2C)
NMAK
NMAK
SP
SP
1735
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