MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1633

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

When a XOFF Pause Frame is generated, the Pause Quanta (Payload Byte P1 and P2) is
filled with the value programmed in the Core register PAUSE_DUR.
The Source Address is set to the MAC address programmed in the Core configuration
registers PADDR1 and PADDR2 and the destination address is set to the fixed Multicast
address 01-80-C2-00-00-01 (0x010000c28001).
When a XON Pause Frame is generated, the Pause Quanta (Payload Byte P1 and P2) is
filled with 0x0000 (Zero Quanta). The Source Address is set to the MAC address
programmed in the Core configuration registers PADDR1 and PADDR2 and the destination
address is set to the fixed Multicast address 01-80-C2-00-00-01 (0x010000c28001).
Pause Frames generated are compliant to the IEEE 802.3 annex 31A&B.
Freescale Semiconductor, Inc.
Although the flow control mechanism should prevent any FIFO
overflow on the MAC Core receive path, the Core receive FIFO
is protected. When an overflow is detected on the receive FIFO,
the current frame is truncated with an error indication set in the
frame status word. The frame should subsequently be discarded
by the user application.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 26-15. Pause Frame Generation Overview
TFC_PAUSE
Generation
Pause
Frame
Note
From Ethernet Line
To Ethernet Line
Programmable
Thereshold
PAUSE_DUR
Chapter 26 Ethernet Controller (ENET)
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