MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1832

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Output Frame Queuing
29.5.2 Cell and Queue Concept
The shared memory is partitioned in 256 byte cells using a 32-bit datapath implementation.
This results in a cell holding 64 32-bit words.
Incoming frames are stored, partitioned in cells, in the shared memory and only the cell
numbers are managed by the individual port queues.
Due to the arbitrary length of incoming frames, the last cell may not be fully utilized. A
frame can spread from one to any number of cells. The number of bytes used in the last cell
is also stored in the queue FIFO together with the individual cell numbers.
Cells can be stored anywhere in the shared memory. A single frame must not necessarily
be stored in consecutive cells but instead can be scattered over the complete memory at
arbitrary positions. The start of a cell is fixed to a 64-word boundary (that is, the memory
start address of a cell is simply the cell # multiplied by 64).
Per port, a queue FIFO is implemented that stores the cell numbers for the frames The
number of bytes used in the last cell is also stored in the queue FIFO together with the
individual cell numbers.
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i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
destination
ports
Figure 29-14. Memory Controller Overview
Control
Write
cell used
free cell#
write data
write address
write enable
write cell#
eop,
last cell length
Factory
Cell
cell# return
Manager
Output
Queue
read address
Dual Port
Memory
Shared
data available
select
read data
read address
select
multiplex)
Manager
(time-
Read
Port
per port control
signals
(sop,eop,mod,
wren)
per port
ready indication
write data
to each
port
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