MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1942

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Behavior During Reset
empty location is available in the receive FIFO and another character is received, the state
of the overrun bit is copied into the receive FIFO along with the received character. The
overrun state is then cleared. The table shows the bit functions of the receive FIFO.
30.2.8 Disabling the FIFOs
FIFOs can be disabled. In this case, the transmit and receive sides of the Application UART
have one-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when
a word has been received and the previous one was not yet read.
In this implementation, the FIFOs are not physically disabled, but the flags are manipulated
to give the illusion of a one-byte register.
30.3 Behavior During Reset
A soft reset (SFTRST) can take multiple clock periods to complete, so do NOT set
CLKGATE when setting SFTRST. The reset process gates the clocks automatically. See
Correct Way to Soft Reset a Block
CLKGATE bit fields.
30.4 Programmable Registers
UARTAPP Hardware Register Format Summary
UARTAPP0 base address is 0x8006A000; UARTAPP1 base address is 0x8006C000;
UARTAPP2 base address is 0x8006E000; UARTAPP3 base address is 0x80070000;
UARTAPP4 base address is 0x80072000
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FIFO bit
7:0
11
10
9
8
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 30-1. Receive FIFO Bit Functions
for additional information on using the SFTRST and
Overrun indicator
Received data
Framing error
Break error
Parity error
Function
Freescale Semiconductor, Inc.