MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 359

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.5.2 AHB to APBH Bridge Control and Status Register 1
The APBH CTRL one provides overall control of the interrupts generated by the AHB to
APBH DMA.
HW_APBH_CTRL1: 0x010
Freescale Semiconductor, Inc.
Reset
APB_BURST_EN
AHB_BURST8_
CLKGATE_
CHANNEL
CLKGATE
Bit
W
SFTRST
R
RSVD0
27 16
Field
15 0
EN
31
30
29
28
15
0
(HW_APBH_CTRL1)
14
0
Set this bit to zero to enable normal APBH DMA operation. Set this bit to one (default) to disable clocking
with the APBH DMA and hold it in its reset (lowest power) state. This bit can be turned on and then off to
reset the APBH DMA block to its default state.
This bit must be set to zero for normal operation. When set to one it gates off the clocks to the block.
Set this bit to one (default) to enable AHB 8-beat burst. Set to zero to disable 8-beat burst on AHB interface.
Set this bit to one to enable apb master do a continous transfers when a device request a burst dma. Set
to zero will treat a burst dma request as 4/8 individual requests.
Reserved, always set to zero.
These bits must be set to zero for normal operation of each channel. When set to one they gate off the
individual clocks to the channels.
0x0001
0x0002
0x0004
0x0008
0x0010
0x0020
0x0040
0x0080
0x0100
0x0200
0x0400
0x0800
0x1000
0x2000
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
SSP0 —
SSP1 —
SSP2 —
SSP3 —
NAND0 —
NAND1 —
NAND2 —
NAND3 —
NAND4 —
NAND5 —
NAND6 —
NAND7 —
HSADC —
LCDIF —
12
0
HW_APBH_CTRL0 field descriptions
11
0
10
0
0
9
CLKGATE_CHANNEL
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
0
8
Description
0
7
0
6
5
0
4
0
0
3
0
2
0
1
0
0
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