MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1233

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Address:
Freescale Semiconductor, Inc.
Reset
Reset
MR1_DATA_3
MR1_DATA_2
Bit
Bit
W
W
R
R
RSVD2
RSVD1
30 16
Field
14 0
RSVD2
RSVD1
31
15
31
15
0
0
HW_DRAM_CTL184
30
14
0
0
Always write zeroes to this field.
Data to program into memory mode register 1 for chip select 3.
Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this EMI:
For DDR1 memories: This parameter correlates to the extended memory mode register (EMR).
For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI
does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000.
For LPDDR1 memories: This parameter has no meaning for this memory type.
This data will be programmed into the appropriate memory register of the DRAM at initialization or when
the write_modereg parameter is set to 'b1.
Always write zeroes to this field.
Data to program into memory mode register 1 for chip select 2.
Holds the memory mode register 1 data for chip select X written during memory initialization. Consult the
memory specification for the fields of this mode register.
The use of this parameter varies based on the memory type connected to this EMI:
For DDR1 memories: This parameter correlates to the extended memory mode register (EMR).
For DDR2 memories: This parameter correlates to the extended memory mode register 1 (EMR1). The EMI
does not support additive latency and therefore the A5:A3 bits should be cleared to 'b000.
For LPDDR1 memories: This parameter has no meaning for this memory type.
This data will be programmed into the appropriate memory register of the DRAM at initialization or when
the write_modereg parameter is set to 'b1.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_DRAM_CTL184 field descriptions
800E_0000h base + 2E0h offset = 800E_02E0h
27
11
0
0
26
10
0
0
25
0
0
9
24
0
0
8
MR1_DATA_3
MR1_DATA_2
Description
23
0
0
7
22
0
0
6
Chapter 14 External Memory Interface (EMI)
21
0
5
0
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
1233
16
0
0
0